Dear Visitor,
Thank you for stopping by gs-asic.
My name is Gvidas Sidlauskas, and I’m a freelance ASIC engineer with over two decades of experience in the semiconductor industry, starting in 2004.
My expertise includes:
- Full-custom analog layout
- DRC / LVS / ANT verification
- Parasitic RLC extraction
- Tool customization and scripting
- Analog and mixed-signal simulation
- ASIC CAD software support
- And more...
If you're interested in collaboration or require support, feel free to reach out via email.
Best regards,
Gvidas Sidlauskas